A major trend in the electronic community is to scale to smaller sizes while integrating more functions onto a single integrated circuit. This demands a process that can offer both high performance analog and digital capabilities, e.g. a BiCMOS process. Some advantages of this process are increased performance, reduced system size and improved system reliability. One result of the trend to higher integration is that supply potentials must also decrease. However, in many analog applications, existing restraints force the supply potentials to remain at values greater than 5, 10 or 20 volts. In some cases the circuits may be required to withstand a bias of 30 volts or greater.
Another trend has been toward a system approach for circuit design and production in a BiCMOS process, in which a standard cell design approach has been adopted. The standard cell design approach allows subcircuits that have been characterized and placed in a library to be used in many designs.
The primary measure of the potential operating voltage of a bipolar NPN transistor is the breakdown voltage between the collector and the emitter with the base opened (BVceo). Typically it is this breakdown voltage that limits the operating voltage. In order to increase the operating voltage of the transistor and thereby the circuit, it becomes necessary to increase the NPN BVceo.
A typical technique for accomplishing this is to simply increase the epitaxial thickness in the bipolar process. Since the thickness of the epitaxial layer would increase, the operating voltage of the circuit would also increase in accordance with the relationship: ##EQU1## Here, BVcbo (bulk) is the thickness-limited breakdown voltage between the N+ buried collector and the base with the emitter opened that occurs at the bottom of the base-collector junction. This portion of the collector-base junction is where the current flows in a vertical bipolar transistor. The planar breakdown is independent of the radius of curvature of the junction, and it is dependent on the epitaxial thickness. The hFE parameter is the common emitter current gain of the transistor, and n is an empirical parameter typically on the order of 3 to 6.
The major disadvantage of increasing the n-type epitaxial thickness in a conventional standard buried collector bipolar process is that as the epitaxial thickness is increased, the p-type isolation must be diffused a greater distance. This also produces an increase in the lateral diffusion of the isolation region, thereby increasing lateral spacing design rules in terms of the distance between each diffusion to the isolation region. Thus, all transistor sizes would be scaled to larger dimensions, even those which do not need to operate to the higher voltage
This is depicted in the attached FIGS. 1a and 1b. A conventional, junction-isolated standard buried collector NPN cross-section is shown in FIG. 1a. The arrow labeled tepi indicates the thickness of the epitaxial layer. The arrows labeled W indicate the distance between diffusion and isolation regions.
FIG. 1b shows a standard buried collector NPN cross-section having an increased epitaxial layer thickness. In FIG. 1b, the arrow labeled tepi+(i) t indicates the thickness of the original epitaxial layer increased by an incremental amount (i) t. The arrows labeled W-ld indicate the distances between the diffusions and isolation regions. The ld term represents an increase in the lateral diffusion of the diffusions and isolation regions. As can be seen by comparing FIG. 1a to FIG. 1b, the lateral spacings between diffusions have been appreciably decreased. As a result, an increase in the lateral spacing design rules of the low voltage devices as well as the high voltage devices would be required, because of the decreased lateral spacing caused by increased lateral diffusion.
Another approach to increase BVceo, indicated by the above relationship, would be to decrease the hFE of the device. This is typically not a very practical solution, however, since the tradeoff between operating voltage and the gain of the device is not desirable due to the degraded performance of the transistor.
The BVceo of an NPN bipolar transistor could also be increased if the N+ buried layer were removed, or its doping level greatly reduced due to the increase in the thickness- limited BVcbo (bulk). However, high collector series resistance and reduced NPN performance would result.
Since bipolar-oriented BiCMOS processes suffer from poor packing densities due to the use of thicker epitaxial layers and the need for deep p+ isolation similar to that shown in FIG. 1b, many advanced BiCMOS processes are CMOS-oriented, where the CMOS process is Nwell-based (i.e. Nwell BiCMOS process). The Nwell BiCMOS process allows the NPN collector region to be self-isolating with the p-type epitaxial layer acting as the isolation region. Since Nwell CMOS processes are commonly used in analog and digital applications, this choice of starting process can minimize the amount of device recharacterization needed after merging bipolar components.
In order to increase the operating voltage of the bipolar transistors in an Nwell BiCMOS process, a similar approach could be taken, i.e. increasing the thickness of the epitaxial layer, resulting in a higher voltage Nwell BiCMOS process.
FIG. 2a shows a standard BiCMOS cross-section. FIG. 2b shows a standard BiCMOS cross-section with a thicker epitaxial layer.
As the epitaxial thickness is increased as shown in FIG. 2b, the Nwell must be driven deeper into the epitaxial layer in order to meet the N+ buried layer. Since the Nwells are used as the wells to house the vertical NPN transistor as well as the PMOS transistors, any alterations made to these regions would affect not only the bipolar devices, but also the CMOS devices. Additional heat cycling would be needed to insure that the up-diffusing N+ buried layer would meet the down-diffusing Nwell. As shown in FIG. 2b by the arrows labeled W-delta 1d, distances both between the Nwells and between the Nwells and adjacent devices are appreciably decreased due to the increased lateral diffusion of the Nwells. This would necessitate increased lateral spacing design rules even for the lower-voltage bipolar and CMOS components.
In a BiCMOS process where it is necessary to increase the voltage of the bipolar devices and yet remain compatible with the standard cell methodology, this would not be acceptable. The purpose of a standard cell methodology is to decrease design times and increase success. Therefore, a technique for obtaining higher-voltage operation must not impact the current low-voltage cells to maintain compatibility with a standard cell methodology.
In a standard bipolar process, there would come a point at which increasing the epitaxial thickness would no longer bring adequate returns in terms of increasing the operating voltage of the transistor. This is referred to as nonthickness-limited break-down between the base and collector. In this case, a conventional technique used to increase the operating voltage of an NPN transistor is to increase the epitaxial resistivity. An increase in resistivity, or decrease in doping level, reduces the slope of the electric field within the epitaxial layer, thereby increasing the BVcbo (bulk) of the device. However, reducing the doping level of the epitaxial layer lowers punch-through voltages within the silicon, necessitating increased distances between diffusions of the same type, leading to design rule increases. Furthermore, in a BiCMOS process the epitaxial layer is used in a different manner (i.e. it forms the isolation between adjacent devices), therefore, this approach would not produce the same result. In fact, increasing the p-type epitaxial resistivity in an Nwell BiCMOS process would act to increase the net Nwell doping level since the Nwell is formed by counter-doping the epitaxial layer with N-type impurities. Thus, this would produce a lower BVcbo (bulk). Nevertheless, if the epitaxial resistivity were changed, the basic BiCMOS devices would be affected making it a nonviable approach for standard cell design strategies.